The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed: Implementations of the present invention, however, are described with respect to a flash electrically-erasable and programmable read-only memory (EEPROM), wherein the storage elements arc floating gates.
A number of architectures are used for non-volatile memories. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, 6,151,248, 6,426,893, and 6,512,263.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the U.S. Pat. No. 6,522,580, that is also hereby incorporated by reference, and references contained therein.
A memory will often have defective portions, either from the manufacturing process or that arise during the operation of the device. A number of techniques exist for managing these defects including error correction coding or remapping portions of the memory, such as described in U.S. Pat. No. 5,602,987, that was incorporated by reference above, or U.S. Pat. Nos. 5,315,541, 5,200,959, and 5,428,621, that are hereby incorporated by reference. For instance, a device is generally thoroughly tested before being shipped. The testing may find a defective portion of the memory that needs to be eliminated. Before shipping the device, the information on these defects is stored on the device, for example in a ROM area of the memory array or in a separate ROM, and at power up it is read by a controller and then used so that the controller can substitute a good portion of the memory for the bad. When reading or writing, the controller will then need to refer to a pointer structure in the controller's memory for this remapping. Having the controller manage this process has the disadvantage of requiring a lot of exchange of information between the controller and the memory portion, and, even within the controller itself, requires the pointer to be read whenever data is transferred. The mapping out of defective elements, such as bad columns in the memory, may be done in a manner that is transparent to the controller. This can make randomly accessing memory elements complicated as any address translation may not take into account mapped out elements.